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LH540235/45
FEATURES * Fast Cycle Times: 20/25/35 ns * Pin-Compatible Drop-In Replacements for
IDT72235B/45B FIFOs
2048 x 18 / 4096 x 18 Synchronous FIFOs
* May be Cascaded for Increased Depth, or
Paralleled for Increased Width
* 16 mA-IOL High-Drive Three-State Outputs * Five Status Flags: Full, Almost-Full, Half-Full,
Almost-Empty, and Empty; `Almost' Flags are Programmable
* Choice of IDT-Compatible or Enhanced Operating
Mode; Selected by an Input Control Signal
* Device Comes Up into One of Two Known Default
States at Reset Depending on the State of the EMODE Control Input: Programming is Allowed, but is not Required
* In Enhanced Operating Mode, Almost-Full,
Half-Full, and Almost-Empty Flags can be Made Completely Synchronous
* In Enhanced Operating Mode, Duplicate Enables
for Interlocked Paralleled FIFO Operation, for 36-Bit Data Width, when Selected and Appropriately Connected
* Internal Memory Array Architecture Based on CMOS * `Synchronous' Enable-Plus-Clock Control at Both
Input Port and Output Port
Dual-Port SRAM Technology, 2048 x 18 or 4096 x 18
* In Enhanced Operating Mode, Disabling
Three-State Outputs May be Made to Suppress Reading
* Independently-Synchronized Operation of Input Port
and Output Port
* Control Inputs Sampled on Rising Clock Edge * Most Control Signals Assertive-LOW for
Noise Immunity
* Data Retransmit Function * TTL/CMOS-Compatible I/O * Space-Saving 68-Pin PLCC Package; Even-Smaller
64-Pin TQFP Package
RS
RESET LOGIC
FL/RT WXI/WEN2 WXO/HF RXI/REN2 RXO/EF2
EXPANSION LOGIC
FIFO MEMORY ARRAY 2048 x 18/4096 x 18
WRITE POINTER WCK WEN WXI/WEN2
READ POINTER RCK OUTPUT PORT CONTROL LOGIC REN RXI/REN2
INPUT PORT CONTROL LOGIC
FF PAF WXO/HF INPUT PORT
DEDICATED AND PROGRAMMABLE STATUS FLAGS OUTPUT PORT PROGRAMMABLE REGISTERS
EF PAE RXO/EF2 OE Q0 - Q17
D0 - D17 LD
EMODE BOLD ITALIC = Enhanced Operating Mode.
540235-1
Figure 1. LH540235/45 Block Diagram
BOLD ITALIC = Enhanced Operating Mode
1
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
FUNCTIONAL DESCRIPTION
NOTE: Throughout this data sheet, a BOLD ITALIC type font is used for all references to Enhanced Operating Mode features which do not function in IDT-Compatible Operating Mode; and also for all references to the retransmit facility (which is not an IDT72235B/45B FIFO feature), even though it may be used - subject to some restrictions - in either of these two operating modes. Thus, readers interested only in using the LH540235/45 FIFOs in IDT-Compatible Operating Mode may skip over BOLD ITALIC sections, if they wish. The LH540235/45 parts are FIFO (First-In, First-Out) memory devices, based on fully-static CMOS dual-port SRAM technology, capable of containing up to 2048 or 4096 18-bit words respectively. They can replace two or more byte-wide FIFOs in many applications, for microprocessorto-microprocessor or microprocessor-to-bus communication. Their architecture supports synchronous operation, tied to two independent free-running clocks at the input and output ports respectively. However, these `clocks' also may be aperiodic, asynchronous `demand' signals. Almost all control-input signals and status-output signals are synchronized to these clocks, to simplify system design. The input and output ports operate altogether independently of each other, unless the FIFO becomes either totally full or else totally empty. Data flow is initiated at a port by the rising edge of its corresponding clock, and is gated by the appropriate edge-sampled enable signals. The following FIFO status flags monitor the extent to which the internal memory has been filled: Full, AlmostFull, Half-Full, Almost-Empty, and Empty. The Almost-Full and Almost-Empty flag offsets are programmable over the entire FIFO depth; but, during a reset operation, each of these is initialized to a default offset value of 12710 FIFO-memory words, from the respective FIFO boundary. If this default offset value is satisfactory, no further programming is required. After a reset operation during which the EMODE control input was not asserted (was HIGH), these FIFOs operate in the IDT-Compatible Operating Mode. In this mode, each part is pin-compatible and functionally-compatible with the IDT72235B/45B part of similar depth and speed grade; and the Control Register is not even accessible or visible to the external-system logic which is controlling the FIFO, although it still performs the same control functions. However, assertion of the EMODE control input during a reset operation leaves Control Register bits 00-05 set, and causes the FIFO to operate in the Enhanced Operating Mode. In essence, asserting EMODE chooses a different default state for the Con-
trol Register. The system optionally then may program the Control Register in any desired manner to activate or deactivate any or all of the Enhanced-Operating-Mode features which it can control, including selectable-clock-edge flag synchronization, and read inhibition when the data outputs are disabled. Whenever EMODE is being asserted, interlockedoperation paralleling also is available, by appropriate interconnection of the FIFO's expansion inputs. The retransmit facility is available during standalone operation, in either IDT-Compatible Operating Mode or Enhanced Operating Mode (see Tables 1 and 2). It is inoperative if the FL/RT input signal is grounded. It is not an IDT72235B/45B feature. The Retransmit control signal causes the internal FIFO read-address pointer to be set back to zero, without affecting the internal FIFO write-address pointer. Thus, the Retransmit control signal also provides a mechanism whereby a block of data delimited by the zero physical address and the current write-address-pointer address may be read out repeatedly, an arbitrary number of times. The only restrictions are that neither the read-address pointer nor the write-address pointer may `wrap around' during this entire process, and that the retransmit facility is not available during depth-cascaded operation, either in IDT-Compatible Operating Mode or in Enhanced Operating Mode (see Tables 1 and 2). Also, the flags behave differently for a short time after a retransmit operation. Otherwise, the retransmit facility is available during standalone operation, in either IDT-Compatible Operating Mode or Enhanced Operating Mode. Note that, when FL/RT is being used as RT, RT is an assertive-HIGH signal, rather than assertive-LOW as it is in most other FIFOs having a retransmit facility. Programming the programmable-flag offsets, the timing synchronization of the various status flags, the optional read-suppression functionality of OE, and the behavior of the pointers which access the offsetvalue registers and the Control Register may be individually controlled by asserting the signal LD, without any reset operation. When LD is being asserted, and writing is being enabled by asserting WEN, some portion of the input bus word D0 - D17 is used at the next rising edge of WCLK to program one or more of the programmable registers on successive write clocks. Likewise, the values programmed into these programmable registers may be read out for verification by asserting LD and REN, with the outputs Q0 - Q17 enabled. Reading out these programmable registers should not be initiated while they are being written into. Table 3 defines the possible modes of operation for loading and reading out the contents of programmable registers.
BOLD ITALIC = Enhanced Operating Mode
2
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
In the Enhanced Operating Mode, coordinated operation of two 18-bit FIFOs as one 36-bit FIFO may be ensured by `interlocked' crosscoupling of the statusflag outputs from each FIFO to the expansion inputs of the other one; that is, FF to WXI/WEN2, and EF to RXI/REN2, in both directions between two paralleled FIFOs. This `interlocked' operation takes effect
automatically, if two paralleled FIFOs are crossconnected in this manner, with the EMODE control input being asserted (LOW) (see Tables 1 and 2, also Figures 28 and 31). IDT-compatible depth cascading no longer is available when operating in this `interlocked-paralleled' mode; however, pipelined depth cascading remains available.
TOP VIEW RCLK REN VCC VSS VSS VCC Q16 VSS Q17 D15 D16 D17 OE RS LD EF Q15 VCC Q14 Q13 VSS Q12 Q11 VCC Q10 Q9 VSS Q8 Q7 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
9 D14 D13 D12 D11 D10 D9 VCC D8 VSS D7 D6 D5 D4 D3 D2 D1 D0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60
EMODE
Q6 Q5 VSS Q4
26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 WEN PAE WXI/WEN2 RXI/REN2 RXO/EF2 WXO/HF WCLK PAF FF Q0 Q1 Q2 VCC Q3 FL/RT VCC VSS
BOLD ITALIC = Enhanced Operating Mode.
540235-2
Figure 2. Pin Connections for PLCC Package
BOLD ITALIC = Enhanced Operating Mode
3
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
64-PIN TQFP
TOP VIEW
RCLK
REN
VCC
VSS
D16
D17
OE
RS
LD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q14 Q13 VSS Q12 Q11 VCC Q10 Q9 VSS Q8 Q7 Q6 Q5 VSS Q4
EF
VCC
VSS
Q16
VSS
Q17
Q15
EMODE
WXI/WEN2
Q1
Q2
WEN
RXO/EF2
WCLK
PAE
VCC
PAF
RXI/REN2
NOTE: BOLD ITALIC = Enhanced operating mode.
540235-34
Figure 3. Pin Connections for Thin Quad Flat Package
SUMMARY OF SIGNALS/PINS
PIN NAME PIN NAME
WXO/HF
FL/RT
D0 - D17 RS
Data Inputs Reset
WXI/WEN2 FF PAF WXO/HF PAE EF RXO/EF2 Q0 - Q17 VCC VSS
EMODE
WCLK WEN RCLK REN OE LD FL/RT RXI/REN2
Enhanced Operating Mode
Write Clock Write Enable Read Clock Read Enable Output Enable Load First Load/Retransmit Read Expansion Input/Read Enable 2
BOLD ITALIC = Enhanced Operating Mode
4
VSS
FF
Q0
Write Expansion Input/Write Enable 2 Full Flag Programmable Almost-Full Flag Write Expansion Output/Half-Full Flag Programmable Almost-Empty Flag Empty Flag Read Expansion Output/Empty Flag 2 Data Outputs Power Ground
Q3
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
PIN LIST
SIGNAL NAME PLCC PIN NO. TQFP PIN NO. SIGNAL NAME PLCC PIN NO. TQFP PIN NO.
RS OE LD REN RCLK D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PAE FT/RT WCLK WEN WXI/WEN2 PAF RXI/REN2 FF WXO/HF RXO/EF2 Q0
1 2 3 4 5 7 8 9 10 11 12 13 14 15 17 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38
57 58 59 60 61 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28
Q1 Q2 Q3 Q4 Q5 Q6
39 41 42 44 46 47 48 49 50 52 53 55 56 58 59 61 63 64 66 6 16 18 32 40 43 45 51 54 57 60 62 65 67 68
29 31 32 34 36 37 33 38 39 41 42 44 45 47 48 50 52 53 54 62 NC NC 22 30 NC 35 40 43 46 49 51 NC 55 56
EMODE
Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 EF VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VCC
BOLD ITALIC = Enhanced Operating Mode
5
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
PIN DESCRIPTIONS
PIN NAME PIN TYPE 1 DESCRIPTION
D0 - D17
Data Inputs
I
Data inputs from an 18-bit bus. When RS is taken LOW, the FIFO's internal read and write pointers are set to address the first physical location of the RAM array; FF, PAF, and HF go HIGH; and PAE and EF go LOW. The programmable-flag-offset registers and the Control Register are set to their default values. (But see the description of EMODE, below.) A reset operation is required before an initial read or write operation after power-up.
RS
Reset
I
EMODE
Enhanced Operating Mode
I
When EMODE is tied LOW, the default setting for Control Register bits 0005 after a reset operation changes to HIGH rather than LOW, thus enabling all Control-Register-controllable Enhanced Operating Mode features, and allowing access to the Control Register for reprogramming or readback (see Tables 1, 2, and 5). If this behavior is desired, EMODE may be grounded; however, Control Register bits 00-06 still may be individually programmed to selectively enable or disable certain of the Enhanced Mode features, even though those features associated with interlocked-paralleled operation always are enabled whenever EMODE is being asserted (see Table 2). Alternatively, EMODE may be tied to VCC, so that the FIFO is functionally IDT-compatible, and the Control Register is not accessible or visible, and all of its bits remain LOW. Controlling EMODE dynamically during system operation is not recommended.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK, whenever WEN (Write Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a programmable register rather than the internal FIFO memory is written into. In the Enhanced Operating Mode, whenever Control Register bit 06 is HIGH, WEN2 is ANDed with WEN to produce an effective internal write-enable signal. 2 When WEN is LOW and LD is HIGH, an 18-bit data word is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO internal memory continues to hold the previous data (see Table 3). Data will not be written into the FIFO if FF is LOW. In the Enhanced Operating Mode, whenever Control Register bit 06 is HIGH, WEN2 is ANDed with WEN to produce an effective internal write-enable signal. 2 Data is read from the FIFO on a LOW-to-HIGH transition of RCLK whenever REN (Read Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a programmable register rather than the internal FIFO memory is read from. In the Enhanced Operating Mode, whenever Control Register bit 06 is HIGH, REN2 is ANDed with REN (and whenever Control Register bit 05 is HIGH, also with OE) to produce an effective internal read-enable signal. 2 When REN is LOW and LD is HIGH, an 18-bit data word is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, and/or also when EF is LOW, the FIFO's output register continues to hold the previous data word, whether or not Q0 - Q17 (the data outputs) are enabled (see Table 3). In the Enhanced Operating Mode, whenever Control Register bit 06 is HIGH, REN2 is ANDed with REN (and whenever Control Register bit 05 is HIGH, also with OE) to produce an effective internal read-enable signal. 2 When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO's outputs are in high-Z (high-impedance) state. In the Enhanced Operating Mode, OE not only continues to control the outputs in this same manner, but also can function as an additional ANDing input to the combined effective read-enable signal, along with REN and REN2, whenever Control Register bit 05 is HIGH (see Table 5). 2
WCLK
Write Clock
I
WEN
Write Enable
I
RCLK
Read Clock
I
REN
Read Enable
I
OE
Output Enable
I
BOLD ITALIC = Enhanced Operating Mode
6
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
PIN DESCRIPTIONS (cont'd)
PIN NAME PIN TYPE 1 DESCRIPTION
LD
Load
I
WEN2
Write Enable 2
I
REN2
Read Enable 2
I
FF
Full Flag
O
PAF
Programmable Almost-Full Flag
O
HF
Half-Full Flag
O
PAE
Programmable Almost-Empty Flag
O
EF
Empty Flag
O
EF2
Q0 - Q17 VCC VSS
Empty Flag 2 Data Outputs Power Ground
O O/Z V V
When LD is LOW, the data word on D0 - D17 (the data inputs) is written into a programmable-flag-offset register, or into the Control Register (when in the Enhanced Operating Mode), on the LOW-to-HIGH transition of WCLK, whenever WEN is LOW (see Table 3). Also, when LD is LOW, a word is read to Q0 - Q17 (the data outputs) from the offset registers and/or the Control Register (when in the Enhanced Operating Mode) on the LOW-to-HIGH transition of RCLK, whenever REN is LOW (see again Table 3, and particularly the Notes following this table). When LD is HIGH, normal FIFO write and read operations are enabled. Tie LOW in Standard Mode, cascading is not supported. In the Enhanded Operating Mode, whenever Control Register Bit06 is HIGH, WXI/WEN2 functions as a second write-enable signal, WEN2, which is ANDed with WEN to produce an effective internal write-enable signal. Tie LOW in Standard Mode. In the Enhanced Operating Mode, whenever Control Register Bit06 is HIGH, RXI/REN2 functions as a second read-enable signal, REN2, which is ANDed with REN to produce an effective internal readenable signal. When FF is LOW, the FIFO is full; further advancement of its internal write-address pointer, and further data writes through its Data Inputs into its internal memory array, are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. When PAF is LOW, the FIFO is `almost full,' based on the almost-full-offset value programmed into the FIFO's Almost-Full Offset Register. The default value of this offset at reset is 12710, measured from `full' (see Table 4). In the IDT-Compatible Operating Mode, PAF is asynchronous. In the Enhanced Operating Mode, PAF is synchronized to WCLK after a reset operation, according to the state of Control Register bit 04 (see Table 5). In the standalone or paralleled configuration, whenever HF is LOW the device is more than half full. In IDT-Compatible Operating Mode, HF is asynchronous; in the Enhanced Operating Mode, HF may be synchronized either to WCLK or to RCLK after a reset operation, according to the state of Control Register bits 02 and 03 (see Table 5). When PAE is LOW, the FIFO is `almost empty,' based on the almost-empty-offset value programmed into the FIFO's Almost-Empty Offset Register. The default value of this offset at reset is 12710, measured from `empty' (see Table 4). In IDTCompatible Operating Mode, PAE is asynchronous. In the Enhanced Operating Mode, PAE is synchronized to RCLK after a reset operation, according to the state of Control Register bit 01. (See Table 5.) When EF is LOW, the FIFO is empty; further advancement of its internal readaddress pointer, and further readout of data words from its internal memory array to its Data Outputs, are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. In the Enhanced Operating Mode, Control Register bit 06 is HIGH, EF2 behaves as an exact duplicate of EF, but delayed by one full cycle of RCLK with respect to EF. Data outputs to drive an 18-bit bus. +3.3 V power-supply pins. 0 V ground pins.
NOTES: 1 I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level 2 The ostensible differences in signal assertiveness are reconciled before ANDing.
BOLD ITALIC = Enhanced Operating Mode
7
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
ABSOLUTE MAXIMUM RATINGS
PARAMETER RATING
+5 V 1.1 k DEVICE UNDER TEST
Supply Voltage to VSS Potential Signal Pin Voltage to VSS Potential DC Output Current 1 Temperature Range with Power Applied 2 Storage Temperature Range Power Dissipation (PLCC Package Limit)
-0.5 V to 7 V -0.5 V to VCC + 0.5 V 75 mA -55C to 125C -65C to 150C 2W
680
30 pF *
NOTES: 1. Only one output may be shorted at a time, for a period not exceeding 30 seconds. 2. Measured with clocks idle.
* INCLUDES JIG AND SCOPE CAPACITANCES
Figure 4. Output Load Circuit
540235-3
OPERATING RANGE
SYMBOL PARAMETER MIN. MAX. UNIT
TA VCC VSS VIL VIH
Temperature, Ambient Supply Voltage Supply Voltage Logic LOW Input Voltage Logic HIGH Input Voltage
0 4.5 0 -0.5 2.0
70 5.5 0 0.8 VCC + 0.5
C V V V V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT
ILI ILO VOH VOL ICC ICC2 ICC3 ICC4
Input Leakage I/O Leakage Output HIGH Voltage Output LOW Voltage Average Operating Supply Current Average Standby Supply Current Power-Down Supply Current
2 2 1,2
VCC = 5.5 V, VIN = 0 V to VCC OE VIH, 0 V VOUT VCC IOH = -8.0 mA IOL = 16.0 mA Measured at fCC = 50 MHz All inputs = VIHMIN (clocks idle) All inputs = VCC - 0.2 V (clocks idle) All inputs = VCC - 0.2 V (clocks at 50 MHz)
-10 -10 2.4
10 10
A A V V mA mA mA mA
0.4 245 25 1 1
Power-Down Supply Current 2
NOTES: 1. Output load is disconnected. 2. ICC, ICC2, and ICC3 are dependent upon actual output loading, and ICC and ICC4 are also dependent on cycle rates. Specified values are with outputs open; and, for ICC and ICC4, operating at minimum cycle times.
AC TEST CONDITIONS
PARAMETER RATING
CAPACITANCE
PARAMETER RATING
Input Pulse Levels Input Rise and Fall Times (10% to 90%) Input Timing Reference Levels Output Timing Reference Levels Output Load, Timing Tests (Figure 5) R1 (Top Resistor) R2 (Bottom Resistor) CL (Load Capacitance)
VSS to 3 V 3 ns 1.5 V 1.5 V 1.1k 680 30 pF
CIN (Input Capacitance) VIN = 0 V COUT (Output Capacitance) VOUT = 0 V
9 pF 9 pF
BOLD ITALIC = Enhanced Operating Mode
8
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER -20 MIN. MAX. -25 MIN. MAX. MIN. -35 MAX.
fCC tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tHF
Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width Reset Setup Time
1
50 2 20 8 8 5 2 5 2 20 12 12 3 25 10 10 6 2 6 2 25 15 15 30
2
40 15 3 35 14 14 7 2 7 2 35 20 20 35 0 0 12 1 12 15 15 17 17 17 1
28.6 20
2 2
Reset Recovery Time
12
Reset to Flag and Output Time Output Enable to Output in Low-Z Output Enable to Output Valid Output Enable to Output in High-Z Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag (IDT-Compatible Operating Mode) Clock to Programmable Almost-Empty Flag (IDT-Compatible Operating Mode) Clock to Half-Full Flag (IDT-Compatible Operating Mode)
2
40
0 9 1 9 12 12 14 14 14
15 15 20 20 23 23 23
tPAFS tPAES tHFS
tXO tXI tXIS tSKEW1 tSKEW2
Clock to Programmable Almost-Full Flag (Enhanced Operating Mode) Clock to Programmable Almost-Empty Flag (Enhanced Operating Mode) Clock to Half-Full Flag (Enhanced Operating Mode)
Clock to Expansion-Out Expansion-In Pulse Width Expansion-In Setup Time Skew Time Between Read Clock and Write Clock for Full Flag 3 Skew Time Between Write Clock and Read Clock for Empty Flag
4
14 14 14
12 8 8 9 9 9 9 11 11
17 17 17
15 13 14 16 16
23 23 23
20
NOTES: 1. Pulse widths less than the stated minimum values may cause incorrect operation. 2. Values are guaranteed by design; not currently tested. 3. These times also apply to the Programmable-Almost-Full and Half-Full flags when they are synchronized to WCLK. 4. These times also apply to the Half-Full and Programmable-Almost-Empty flags when they are synchronized to RCLK.
BOLD ITALIC = Enhanced Operating Mode
Rev. B, 8/8/96
9
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES
Table 1. Grouping-Mode Determination During a Reset Operation 5
EMODE
WXI/WEN2 RXI/REN2 FL/RT MODE WXO/HF USAGE WXI/WEN2 USAGE RXI/REN2 USAGE FL/RT USAGE RXO/EF2 USAGE
H1 H1 H H H
H H H L
H H L H
H L X X H3 L3
3
Cascaded Slave 2 Cascaded Master 2 (Reserved) (Reserved) (Not Allowed During Reset) Standalone
WXO WXO
- -
WXI WXI
- -
RXI RXI
- -
FL FL
- -
RXO RXO
- -
L
L
(HF)
(none)
(none)
(RT)
(none)
H
L
L
HF
(none)
(none)
RT
(none)
L
X
X
H
(Not Allowed During Reset) Interlocked Paralleled 4
(HF)
(WEN2)
(REN2)
(RT)
(EF2)
L
X
X
L3
HF
WEN2
REN2
RT
EF2
NOTES: 1. In IDT-compatible cascading, a reset operation forces WXO/HF and RXO/EF2 HIGH for the nth FIFO, thus forcing WXI/WEN2 and RXI/REN2 HIGH for the (n + 1)st FIFO. 2. The terms `master' and `slave' refer to IDT-compatible cascading. In pipelined cascading4, there is no such distinction. 3. Once grouping mode has been determined during a reset operation, FL/RT then may go HIGH to activate a retransmit operation. 4. EMODE must be asserted for access to the Control Register to be enabled. Also, FIFOs being used in a pipelined-cascading configuration should be in Interlocked Paralleled mode. 5. Setup-time and recovery-time specifications apply during a reset operation.
Table 2. Expansion-Pin Usage According to Grouping Mode
IDT-COMPATIBLE OPERATING MODE I/O PIN DEPTH-CASCADED MASTER DEPTH-CASCADED SLAVE
STANDALONE
ENHANCED OPERATING MODE
INTERLOCKED PARALLELED
I O I O I
WXI /WEN2 WXO/HF RXI/REN2 RXO/EF2 FL/RT
From WXO ((n-1)st FIFO) To WXI ((n+1)st FIFO) From RXO ((n-1)st FIFO) To RXI ((n+1)st FIFO) Grounded (Logic LOW)
From WXO ((n-1)st FIFO) To WXI ((n+1)st FIFO) From RXO ((n-1)st FIFO) To RXI ((n+1)st FIFO) Logic HIGH
Grounded Becomes HF Grounded Unused
From FF (other FIFO) Becomes HF From EF (other FIFO) Becomes EF2
1
Becomes RT
Becomes RT1
NOTE: 1. FL/RT may be grounded if the Retransmit facility is not being used.
BOLD ITALIC = Enhanced Operating Mode
10
2048 x 18/4096 x 18 Synchronous FIFOs Table 3. Selection of Read and Write Operations
LD WEN
3,4
LH540235/45
REN
3,4
WCLK
RCLK
ACTION
L L L L L L H H H H H H H H
X L L H H H L X L H X X L H
X L H H L H X L X X L H L H
- X X X - X X X - X
- X X X X X - X - X
No operation. Illegal combination, which will cause errors. Write to a programmable register. 1 Hold present value of programmable-register write counter, and do not write. 2 Read from a programmable register. 1 Hold present value of programmable-register read counter, and do not read. 2 Normal FIFO write operation. Normal FIFO read operation. No write operation. No write operation. No read operation. No read operation. No operation. No operation.
KEY: H = Logic `HIGH'; L = Logic `LOW'; X = `Don't-care' (logic `HIGH,' logic `LOW,' or any transition); = A `LOW'-to-`HIGH' transition; - = Any condition EXCEPT a `LOW'-to-`HIGH' transition. NOTES: 1. The selection of a programmable register to be written or read is controlled by two simple state machines. One state machine controls the selection for writing; the other state machine controls the selection for reading. These two state machines operate independently of each other. Both state machines are reset to point to Word 0 by a reset operation. In the Enhanced Operating Mode, if Control Register bit 00 is set, both state machines are also reset to point to Word 0 by deassertion of LD after LD has been asserted (that is, by a rising edge of LD), followed by a valid memory array write cycle for the writing-control state machine and/or by a valid memory array read cycle for the reading-control state machine. 2. The order of the two programmable registers which are accessible in IDT-Compatible Operating Mode, as selected by either state machine, is always: Word 0: Almost-Empty Offset Register Word 1: Almost-Full Offset Register Word 0: Almost-Empty Offset Register ... (repeats indefinitely) ... The order of the three programmable registers which are accessible in Enhanced Operating Mode, as selected by either state machine, is always: Word 0: Almost-Empty Offset Register Word 1: Almost-Full Offset Register Word 2: Control Register Word 0: Almost-Empty Offset Register ... (repeats indefinitely) ... Note that, in IDT-Compatible Operating Mode, Word 2 is not accessed; Word 0 and Word 1 alternate. 3. After normal FIFO operation has begun, writing new contents into either of the offset registers should only be done when the FIFO is empty. 4. WEN2, REN2, and OE may be ANDed terms in the enabling of read and write operations, according to the state of the EMODE control input and of Control Register bit 05.
BOLD ITALIC = Enhanced Operating Mode
11
LH540235/45 Table 4. Status Flags
NUMBER OF UNREAD DATA WORDS PRESENT WITHIN FIFO 1, 2 2048 x 18 FIFO 4096 x 18 FIFO FULL FLAG FF
2048 x 18/4096 x 18 Synchronous FIFOs
MIDDLE FLAGS PAF HF PAE
EMPTY FLAG EF
0 1 to q (q + 1) to 1024 1025 to (2048 - (p + 1)) (2048 - p) to 2047 2048
0 1 to q (q + 1) to 2048 2049 to (4096 - (p + 1)) (4096 - p) to 4095 4096
H H H H H L
H H H H L L
H H H L L L
L L H H H H
L H H H H H
NOTES: 1. q = Programmable-Almost-Empty Offset value. (Default value: q = 127.) 2. p = Programmable-Almost-Full Offset value. (Default value: p = 127.) 3. Only 11 (2048 x 18), or all 12 (4096 x 18), of the 12 offset-value-register bits should be programmed. The unneeded most-significant-end 2048 x 18 bit should be LOW (zero). 4. The flag output is delayed by one full clock cycle in Enhanced Operating Mode, when synchronous operation is specified for intermediate flags.
BOLD ITALIC = Enhanced Operating Mode
12
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont'd)
Table 5. Control-Register Format
COMMAND REGISTER BITS VALUE AFTER RESET CODE EMODE = H EMODE = L FLAG AFFECTED, IF ANY DESCRIPTION NOTES
L
00 H
L
H
-
Deassertion of LD does not reset the programmableregister write pointer and read pointer. Deassertion of LD resets the programmable-register write pointer and read pointer to address Word 0, the Programmable-AlmostEmpty-Flag-Offset Register. The change takes effect after a valid write operation or a valid read operation, respectively, to the memory array. Set by RCLK, reset by WCLK. Set and reset by RCLK. Set by WCLK, reset by RCLK.
IDT-compatible addressing of programmable registers.
Non-ambiguous addressing of programmable registers.
01
L H
LL
L
H
PAE
Asynchronous flag clocking. Synchronous flag clocking. Asynchronous flag clocking. Synchronous flag clocking at output port. Synchronous flag clocking at input port. Asynchronous flag clocking. Synchronous flag clocking. Allows the read-address pointer to advance even when Q0 - Q17 are not driving the output bus. Inhibits the read-address pointer from advancing when Q0 - Q17 are not driving the output bus; thus, guards against data loss. Future use to control depth cascading and interlocked paralleling. Reserved.
03, 02
LH HL, HH
LL
HH
HF
Set and reset by RCLK. Set and reset by WCLK.
04
L H L
L
H
PAF
Set by WCLK, reset by RCLK. Set and reset by WCLK. OE has no effect on an internal read operation, apart from disabling the outputs. Deassertion of OE inhibits a read operation; whenever the data outputs Q0 - Q17 are in the high-Z state, the read pointer does not advance. Reserved. Reserved.
05 H
L
H
-
L 06 11, 10, 09, 08, 07 H LLLLL L LLLLL L LLLLL
- -
NOTES: 1. When EMODE is HIGH, and Control Register bits 00-05 are LOW, the FIFO behaves in a manner functionally equivalent to the IDT72235B/45B FIFO of similar depth and speed grade. Under these conditions, the Control Register is not visible or accessible to the external system which includes the FIFO. 2. If EMODE is not asserted (is HIGH), Control Register bits 00-05 remain LOW after a reset operation. However, if EMODE is asserted (is LOW) during a reset operation, Control Register bits 00-05 are forced HIGH, and remain HIGH until changed. Control Register bits 06-11 are unaffected by EMODE.
BOLD ITALIC = Enhanced Operating Mode
13
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs WRITE CLOCK (WCLK) A rising edge (LOW-to-HIGH transition) of WCLK initiates a FIFO write cycle if LD is HIGH, or a programmable-register write cycle if LD is LOW. The 18 data inputs, and all input-side synchronous control inputs, must meet setup and hold times with respect to the rising edge of WCLK. The input-side status flags are meaningful after specified time intervals, following a rising edge of WCLK. Conceptually, the WCLK input receives a free-running, periodic `clock' waveform, which is used to control other signals which are edge-sensitive. However, there actually is not any absolute requirement that the WCLK waveform must be periodic. An `asynchronous' mode of operation is in fact possible, if WEN is continuously asserted (that is, is continuously held LOW), and WCLK receives aperiodic `clock' pulses of suitable duration. There likewise is no requirement that WCLK must have any particular synchronization relation to the read clock RCLK. These two clock inputs may in fact receive the same `clock' signal; or they may receive totally-different signals, which are not synchronized to each other in any way. WRITE ENABLE (WEN) Whenever WEN is being asserted (is LOW) and LD is HIGH, and the FIFO is not full, an 18-bit data word is loaded into the effective input register for the memory array at every WCLK rising edge (LOW-to-HIGH transition). Data words are stored into the two-port memory array sequentially, regardless of any ongoing read operation. Whenever WEN is not being asserted (is HIGH), the input register retains whatever data word it contained previously, and no new data word gets loaded into the memory array. To prevent overrunning the internal FIFO boundaries, further write operations are inhibited whenever the Full Flag (FF) is being asserted (is LOW). If a valid read operation then occurs, upon the completion of that read cycle FF again goes HIGH after a time tWFF, and another write operation is allowed to begin whenever WCLK makes another LOW-to-HIGH transition. Effectively, WEN is overridden by FF; thus, during normal FIFO operation, WEN has no effect when the FIFO is full.
Data Inputs
DATA IN (D0 - D17) Data, programmable-flag-offset values, and ControlRegister codes are input to the FIFO as 18-bit words on D0 - D17. Unused bit positions in offset-value and Control-Register words should be zero-filled.
Control Inputs
RESET (RS) The FIFO is reset whenever the asynchronous Reset (RS) input is taken to a LOW state. A reset operation is required after power-up, before the first write operation may occur. The state of the FIFO is fully defined after a reset operation. If the default values which are entered into the Programmable-Flag-Offset-Value Registers and the Control Register by a reset operation are acceptable, then no device programming is required. A reset operation initializes the FIFO's internal read-address and write-address pointers to the FIFO's first physical memory location. The five status flags, FF, PAF, HF, PAE, and EF, are updated to indicate that the FIFO is completely empty; thus, the first three of these are reset to HIGH, and the last two are reset to LOW. The flag-offset values for PAF and PAE each are initialized to 12710. If EMODE is not being asserted (i.e., if EMODE is HIGH), all Control Register bits are initialized to LOW, to configure the FIFO to operate in the IDT72235B/45B-Compatible Operating Mode. Until a write operation occurs, the data outputs D0 - D17 all are LOW whenever OE is LOW.
ENHANCED OPERATING MODE (EMODE) Whenever EMODE is asserted during a reset operation, Control Register bits 00-05 remain HIGH rather than LOW after the completion of the reset operation. Thus, EMODE has the effect of activating all of the Enhanced-Operating-Mode features during a reset operation. Subsequently, they may be individually disabled or re-enabled by changing the setting of Control-Register bits. The behavior of these Enhanced-Operating-Mode features is described in Table 5. For permanent Enhanced-Operating-Mode operation, EMODE must be grounded; dynamic control of EMODE during system operation is not recommended. Asserting EMODE during a reset operation also causes WXI/WEN2 to be configured as WEN2, and RXI/REN2 to be configured as REN2, to support interlocked-paralleled operation of two FIFOs `side by side' (see Figure 28). Additionally, RXO/EF2 is configured as EF2, which duplicates the EF signal with one extra RCK cycle delay, in order to provide proper timing for `pipelined' cascaded operation.
In the Enhanced Operating Mode, WXI/WEN2 functions as WEN2, an additional duplicate (albeit assertive-HIGH) write-enable input, in order to provide an`interlocking' mechanism for reliable synchronization of two paralleled FIFOs. To control writing, WEN2 is ANDed with WEN; this logic-AND function (WEN * WEN2) then behaves like WEN in the foregoing description.
BOLD ITALIC = Enhanced Operating Mode
14
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont'd)
READ CLOCK (RCLK) A rising edge (LOW-to-HIGH transition) of RCLK initiates a FIFO read cycle if LD is HIGH, or a programmable-register read cycle if LD is LOW. All output-side synchronous control inputs must meet setup and hold times with respect to the rising edge of RCLK. The 18 data outputs, and the output-side status flags, are meaningful after specified time intervals, following a rising edge of RCLK. Conceptually, the RCLK input receives a free-running, periodic `clock' waveform, which is used to control other signals which are edge-sensitive. However, there actually is not any absolute requirement that the RCLK waveform must be periodic. An `asynchronous' mode of operation is in fact possible, if REN is continuously asserted (that is, is continuously held LOW), and RCLK receives aperiodic `clock' pulses of suitable duration. There likewise is no requirement that RCLK must have any particular synchronization relation to the write clock WCLK. These two clock inputs may in fact receive the same `clock' signal; or they may receive totally-different signals, which are not synchronized to each other in any way. READ ENABLE (REN) Whenever REN is being asserted (is LOW), and the FIFO is not empty, an 18-bit data word is loaded into the output register from the memory array at every RCLK rising edge (LOW-to-HIGH transition). Data words are read from the two-port memory array sequentially, regardless of any ongoing write operation. Whenever REN is not being asserted (is HIGH), the output register retains whatever data word it contained previously, and no new data word gets loaded into it from the memory array. To prevent underrunning the internal FIFO boundaries, further read operations are inhibited whenever the Empty Flag (EF) is being asserted (is LOW). If a valid write operation then occurs, upon the completion of that write cycle EF again goes HIGH after a time tREF, and another read operation is allowed to begin whenever RCLK makes another LOW-to-HIGH transition. Effectively, REN is overridden by EF; thus, during normal FIFO operation, REN has no effect when the FIFO is empty. In the Enhanced Operating Mode, one (or, sometimes two) additional read-enable inputs may be ANDed with REN to control reading, depending on the state of Control-Register bit 05. The additional read-enable input(s) are REN2 (and OE).
Also in the Enhanced Operating Mode, RXI/REN2 functions as REN2, an additional duplicate (albeit assertive-HIGH) Read-Enable input, in order to provide an `interlocking' mechanism for reliable synchronization of two paralleled FIFOs. Also, if Control Register bit 05 is HIGH, OE takes on the extra role of serving as yet another duplicate read-enable input, in addition to its usual function of controlling the FIFO's data outputs, in order to inhibit further read operations whenever the FIFO's data outputs are disabled, and thereby to prevent data loss under some circumstances.
OUTPUT ENABLE (OE) OE is an assertive-LOW, asynchronous, output enable. In the IDT-Compatible Operating Mode, OE has only the effect of enabling or disabling the data outputs Q0 - Q17. That is, disabling Q0 - Q17 does not inhibit a read operation, for data being transmitted to the output register; the same data will remain available later, when the outputs are again enabled, unless subsequently overwritten. When Q0 - Q17 are enabled, each of these 18 data outputs is in a normal HIGH or LOW state, according to the bit pattern of the data word in the output register. When Q0 - Q17 are disabled, each of these outputs is in the high-Z (high-impedance) state. In the Enhanced Operating Mode, if Control Register bit 05 is HIGH, OE behaves as an additional read-enable control input, as well as enabling and disabling the data outputs Q0 - Q17. Under these circumstances, incrementing the read-address pointer is inhibited whenever Q0 - Q17 are in the high-Z state. Thus, `reading' successive words which fail ever to reach the outputs is prevented, as a safeguard against data loss. LOAD (LD) The Sharp LH540235/45 FIFOs contain three 18-bit programmable registers. The contents of these three registers may be loaded with data from the data inputs D0 - D17, or read out onto the data outputs Q0 - Q17. The first two registers are the Programmable-Flag-OffsetValue Registers, for the Programmable Almost-Empty Flag (PAE) and the Programmable Almost-Full Flag (PAF) respectively. The third register is the Control Register, which includes several configuration-control bits for selectively enabling and disabling Sharp's Enhanced-Operating-Mode features.
BOLD ITALIC = Enhanced Operating Mode
15
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
WORD 0
3
PROGRAMMABLE-ALMOST-EMPTY-FLAG-OFFSET VALUE 1, 2
17
12
11
10
0
WORD 1
3
PROGRAMMABLE-ALMOST-FULL-FLAG-OFFSET VALUE 1, 2
17
12
11
10
0
CONTROL REGISTER 4, 5 WORD 2 Reserved for future use. 17 CONTROL-REGISTER BITS: 6 Future use to control depth cascading and interlocked paralleling. 5 Enables suppressing reading whenever data outputs are disabled. 4 Makes PAF synchronous. 3 2 Makes HF synchronous. (See the Control-Register Format table for the encoding of bits 02-03.) 1 Makes PAE synchronous. 0 Selects reinitialized addressing of the programmable registers.
NOTES: 1. Default offset values all are 12710 = 7F16. 2. Bits 11-17 (LH540235) or bits 12-17 (LH540245) of both offset-value registers should in all cases be programmed LOW (zero). 3. This bit position is used for offset values in the LH540245 only. In the LH540235, it always should be programmed LOW. 4. See the Control-Register Format table for the default states of the Control Register, for EMODE = HIGH (IDT-Compatible Operating Mode) and for EMODE = LOW (Enhanced Operating Mode). The Control Register is not accessible or visible in IDT-Compatible Operating Mode. 5. The assertion of EMODE (LOW) forces Control Register bits 00-05 HIGH during a reset operation. After that, these bits may be programmed at will. = Reserved. Do not load with non-zero information.
6 7 6
5 5
4 4
3 3
2 2
1 1
0 0
12
11
See Table 5 for a more complete description of these effects.
BOLD ITALIC = Enhanced Operating Mode.
540235-4
Figure 5. Programmable Registers None of these three registers makes use of all of its available 18 bits. Figure 6 shows which bit positions of each register are operational. The two ProgrammableFlag-Offset-Value Registers each contain an offset value in bits 0-10 (LH540235) or bits 0-11 (LH540245); bits 11-17 (LH540235) or bits 12-17 (LH540245) are unused. The default values for both offsets are 12710. The Control Register configuration is shown in Figure 6 and in Table 5. For the Control Register, in the IDT-Compatible Operating Mode, with EMODE deasserted (HIGH), the default value for all Control-Register bits is zero (LOW). In the Enhanced Operating Mode, with EMODE asserted (LOW), the default value for bits 00-05 is HIGH, and the default value for bits 06-11 is LOW.
BOLD ITALIC = Enhanced Operating Mode
Whenever LD and WEN are simultaneously being asserted (are both LOW), the 18-bit data word from the data inputs D0 - D17 is written into the ProgrammableAlmost-Empty-Flag-Offset-Value Register at the first rising edge (LOW-to-HIGH transition) of the write clock (WCLK). (See Table 3.) If LD and WEN continue to be simultaneously asserted, another 18-bit data word from the data inputs D0 - D17 is written into the Programmable-Almost-Full-Flag-Offset-Value Register at the second rising edge of WCLK.
16
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont'd)
What happens next is determined by the state of the EMODE control input. If it is deasserted (HIGH), the next 18-bit word from the data inputs D0 - D17 is written back into the Programmable-Almost-Empty-Flag-Offset-Value Register again. But, if EMODE is asserted (LOW), then still another 18-bit data word from the data inputs D0 - D17 is written into the Control Register at the third rising edge of WCLK. At the fourth rising edge of WCLK, writing again occurs to the Programmable-AlmostEmpty-Flag-Offset-Value Register; and the same three-step writing sequence gets repeated on subsequent WCLK rising edges. The lower 11 bits of these offset-value words are made use of by the 2048-word LH540235, and the lower 12 bits by the 4096-word LH540245. Six active bits are used for the Control Register, by both the LH540235 and the LH540245. There is no restriction on the values which may occur in these offset-value and Control-Register fields. However, reserved bit positions must be encoded LOW, in order to maintain forward compatibility. Writing contents to these two or three programmable registers does not have to occur all at one time, or to be effected by one single sequence of steps. Whenever LD is being asserted (is LOW) but WEN is not being asserted (is HIGH), the FIFO's internal programmable-registerwrite-address pointer maintains its present value, without any writing actually taking place at each rising edge of WCLK (see Table 3). Thus, for instance, one or two programmable registers may be written, after which the FIFO may be returned to normal FIFO-array-read/write operation by deasserting LD (to HIGH). Likewise, whenever LD and REN are simultaneously being asserted (are both LOW) the 18-bit data word (zero-filled as necessary) from the Programmable-Almost-Empty-Flag-Offset-Value Register is read to the data outputs Q0 - Q17 at the first rising edge (LOW-toHIGH transition) of the read clock (RCLK) (see Table 3). If LD and REN continue to be simultaneously asserted, another 18-bit data word from the Programmable-AlmostFull-Flag-Offset-Value Register is read to the data outputs Q0 - Q17 at the second rising edge of RCLK. What happens next is determined by the state of the EMODE control input. If it is deasserted (HIGH), the next 18-bit word again comes from the Programmable-AlmostEmpty-Flag-Offset-Value Register; it is read to the data outputs Q0 - Q17. But, if EMODE is asserted (LOW), then the next 18-bit data word instead comes from the Control Register; it is read to the data outputs Q0 - Q17 at the third rising edge of RCLK. At the fourth rising edge of RCLK, reading again occurs from the Programmable-Almost-Empty-Flag-Offset-Value Register; and
BOLD ITALIC = Enhanced Operating Mode
the same three-step reading sequence gets repeated on subsequent RCLK rising edges.
Reading contents from these two or three programmable registers does not have to occur all at one time, or to be effected by one single sequence of steps. Whenever LD is being asserted (is LOW) but REN is not being asserted (is HIGH), the FIFO's internal programmableregister-read-address pointer maintains its present value, without any reading actually taking place at each rising edge of RCLK. (See Table 3.) Thus, for instance, one or two programmable registers may be read, after which the FIFO may be returned to normal FIFO-array-read/write operation by deasserting LD (to HIGH). To ensure correct operation, the simultaneous reading and writing of a register should be avoided. FIRST LOAD/RETRANSMIT (FL/RT) FL/RT is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are WXI/WEN2, RXI/REN2, and EMODE. There are four possible grouping modes: standalone, interlocked paralleled, cascaded `master' or `first-load,' and cascaded `slave.' The designations `master' and `slave' pertain to IDT-compatible depth cascading. Tables 1 and 2 show the signal encodings which select each grouping mode. In standalone or paralleled operation, the FL/RT pin should be grounded for strict IDT72235B/45B-compatible operation. However, if it is taken HIGH, regardless of the state of the EMODE control input, the FIFO's internal read-address pointer is reset to address the FIFO's first physical memory location, without the other usual reset actions being taken; in particular, the FIFO's internal write-address pointer is unaffected. Subsequent read operations may then again read out the same block of data, delimited by the FIFO's first physical memory location and the current value of the write pointer, as was read out previously. There is no limit on the number of times that a block of data may be retransmitted. The only restrictions are that neither the read-address pointer nor the write-address pointer may `wrap around' and address the FIFO's first physical memory location a second time during the retransmission process, and that the retransmit facility is unavailable during cascaded operation. In IDT-compatible cascaded operation, FL/RT is grounded for the `master' or `first-load' FIFO, to distinguish it from the other `slave' FIFOs in the cascade, which must all have their FL/RT inputs HIGH during a reset operation (see again Tables 1 and 2). The cascade will not operate correctly either without any `master' FIFO, or with more than one `master' FIFO.
17
LH540235/45 WRITE EXPANSION INPUT/WRITE ENABLE 2 (WXI/WEN2) WXI/WEN2 is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are FL/RT, RXI/REN2, and EMODE. There are four possible grouping modes: standalone, interlocked paralleled, cascaded `master' or `first-load,' and cascaded `slave.' The designations `master' and `slave' pertain to IDT-compatible depth cascading. Tables 1 and 2 show the signal encodings which select each grouping mode. In standalone operation, WXI/WEN2 and RXI/REN2 both must be grounded so that the FIFO comes up in the standalone grouping mode after a reset operation. In interlocked-paralleled operation, WXI/WEN2 is tied to FF of the other paralleled FIFO, and RXI/REN2 is tied to EF of that same other FIFO. This interconnection scheme ensures that both FIFOs will operate together, and remain coordinated, regardless of timing skews. In cascaded operation, WXI/WEN2 is connected to the WXO (Write Expansion Output; actually WXO/HF) output of the previous FIFO in the cascade. RXI/REN2 is likewise connected to the RXO (Read Expansion Output; actually RXO/EF2) output of that previous FIFO. A reset operation forces WXO/HF and RXO/EF2 HIGH for each FIFO; consequently, all FIFOs with their WXI/WEN2 and RXI/REN2 inputs thus connected come up in one of the two cascaded grouping modes, according to whether their FL/RT inputs are grounded or tied HIGH (see Tables 1 and 2). READ EXPANSION INPUT/READ ENABLE 2 (RXI/REN2) RXI/REN2 is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are FL/RT, WXI/WEN2, and EMODE. There are four possible grouping modes: standalone, interlocked-paralleled, cascaded `master' or `first-load,' and cascaded `slave.' The designations `master' and `slave' pertain to IDT-compatible depth cascading. Tables 1 and 2 show the signal encodings which select each grouping mode. In standalone operation, WXI/WEN2 and RXI/REN2 both must be grounded, so that the FIFO comes up in the standalone grouping mode after a reset operation. In interlocked-paralleled operation, WXI/WEN2 is tied to FF of the other paralleled FIFO, and RXI/REN2 is tied to EF of that same other FIFO. This interconnection scheme ensures that both FIFOs will operate together, and remain coordinated, regardless of timing skews.
2048 x 18/4096 x 18 Synchronous FIFOs In cascaded operation, RXI/REN2 is connected to RXO (Read Expansion Output; actually RXO/EF2)) of the previous FIFO in the cascade. WXI/WEN2 is likewise connected to WXO (Write Expansion Output; actually WXO/HF) output of that previous FIFO. A reset operation forces RXO/EF2 and WXO/HF HIGH for each FIFO; consequently, all FIFOs with their RXI/REN2 and WXI/WEN2 inputs thus connected come up in one of the two IDT-compatible cascaded grouping modes, according to whether their FL/RT inputs are grounded or tied HIGH (see again Tables 1 and 2).
Data Outputs
DATA OUT (Q0 - Q17) Data, programmable-flag-offset values, and ControlRegister codes are output from the FIFO as 18-bit words on Q0 - Q17. Unused bit positions in offset-value words and Control-Register words are zero-filled.
Control/Status Outputs
FULL FLAG (FF) FF goes LOW whenever the FIFO is completely full. That is, whenever the FIFO's internal write pointer has completely caught up with its internal read pointer; so that, if another word were to be written, it would have to overwrite the unread word which is now in position for reading out by the next requested read operation. Under these conditions, the FIFO is filled to its nominal capacity, which is 2048 18-bit words for the LH540235 or 4096 18-bit words for the LH540245 respectively. Write operations are inhibited whenever FF is LOW, regardless of the assertion or deassertion of Write Enable (WEN). If the FIFO has been reset by asserting RS (LOW), FF initially is HIGH. But, whenever no read operations have been performed since the completion of the reset operation, FF goes LOW after 2048 write operations for the LH540235, or after 4096 write operations for the LH540245 (see Table 4). FF gets updated after a LOW-to-HIGH transition of the Write Clock (WCLK). PROGRAMMABLE ALMOST-FULL FLAG (PAF) PAF goes LOW whenever the FIFO is `almost' full; that is, whenever subtracting the value of the FIFO's internal read pointer from the value of its internal write pointer yields a difference which is less than the value of the Programmable-Almost-Full-Flag Offset `p.' The subtraction is performed using modular arithmetic, modulo the total nominal number of 18-bit words in the FIFO's physical memory, which is 2048 for the LH540235 or 4096 for the LH540245 respectively.
BOLD ITALIC = Enhanced Operating Mode
18
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45 writing. Otherwise, WXO remains constantly HIGH whenever the FIFO is operating in cascaded mode. This LOWgoing WXO pulse serves as a `write token' in the `token-passing' FIFO-cascading scheme; it is passed on to the next FIFO in the ring via its WXI input. When this next FIFO receives the write token, it is activated for writing at the next valid WCLK. The foregoing description applies both to the `first-load' or `master' FIFO in the ring, and to any and all `slave' FIFOs in the ring. However, WXO has no necessary function for FIFOs operating in the `standalone' mode. Consequently, in that mode, the same output pin is used for HF; it follows that HF is not available as an output from any FIFO which is operating in the IDT-compatible cascaded mode. A FIFO is initialized into `cascaded master' mode, into `cascaded slave' mode, into interlocked-paralleled mode, or into standalone mode according to the state of its WXI/WEN2, RXI/REN2, and FL/RT control inputs during a reset operation, and of EMODE (see Table 1, Table 2, and Table 5). In standalone or interlocked-paralleled operation, HF goes LOW whenever the FIFO is more than half full; that is, whenever subtracting the value of the FIFO's internal read pointer from the value of its internal write pointer yields a difference which is less than half of the total nominal number of 18-bit words in the FIFO's physical memory, which is 1024 for the LH540235 or 2048 for the LH540245 respectively (see Table 4). The subtraction is performed using modular arithmetic, modulo this total nominal number of words, which is 2048 for the LH540235 or 4096 for the LH540245 respectively. If the FIFO has been reset by asserting RS (LOW), and it is operating in standalone mode or in interlocked-paralleled mode, and no read operations have been performed since the completion of the reset operation, HF goes LOW after 1025 write operations for the LH540235, or after 2049 write operations for the LH540245 (see again Table 4). In the IDT-Compatible Operating Mode, HF changes from HIGH to LOW only after a LOW-to-HIGH transition of the Write Clock WCLK, and from LOW to HIGH only after a LOW-to-HIGH transition of the Read Clock RCLK. Thus, in this operating mode, HF behaves as an `asynchronous flag.'
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont'd)
The default value of `p' after the completion of a reset operation is 12710. However, `p' may be set to any value which does not exceed this total nominal number of words for the device, as explained in the description of Load (LD). If the FIFO has been reset by asserting RS (LOW), and no read operations have been performed since the completion of the reset operation, PAF goes LOW after (2048-p) write operations for the LH540235, or after (4096-p) write operations for the LH540245 (see Table 4). If p is still at its default value, PAF is LOW whenever the FIFO is from seven-eighths full to completely full. In the IDT-Compatible Operating Mode, PAF changes from HIGH to LOW only after a LOW-to-HIGH transition of the Write Clock WCLK, and from LOW to HIGH only after a LOW-to-HIGH transition of the Read Clock RCLK. Thus, in this operating mode, PAF behaves as an `asynchronous flag.'
In the Enhanced Operating Mode, on the other hand, PAF gets updated only after a LOW-to-HIGH transition of the Write Clock WCLK, and thus behaves as a `synchronous flag,' whenever Control Register bit 04 is HIGH (see Table 5).
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF) WXO/HF is a dual-purpose signal. In `standalone' operation, it behaves as a Half-Full Flag (HF), in accordance with Table 4. In IDT-compatible `cascaded' operation, it behaves as a Write Expansion Output (WXO) signal to coordinate writing operations with the next FIFO in the cascade. Under these same conditions, also, the dual-purpose WXI/WEN2 and RXI/REN2 inputs behave as Write Expansion Input (WXI) and Read Expansion Input (RXI) signals respectively. When two or more LH540235 or LH540245 FIFOs are `cascaded' to operate as a deeper `effective FIFO,' in an IDT-style `daisy-chain' ring configuration, the Write Expansion Input (WXI) of each FIFO is connected to WXO of the previous FIFO in the ring, with WXI of the `first-load' or `master' FIFO being connected to WXO of the last FIFO so as to complete the ring. Similar connections are made for each FIFO in the ring, parallel to these WXO-to-WXI connections, for Read Expansion Input (RXI) and Read Expansion Output (RXO/EF2, when it is behaving as RXO). When the last physical location has been written in a FIFO operating in cascaded mode, a LOW-going pulse is emitted by that FIFO on its WXO output, and the FIFO is deactivated for writing at the next valid WCLK; and the next FIFO in the ring is simultaneously activated for
BOLD ITALIC = Enhanced Operating Mode
In the Enhanced Operating Mode, on the other hand, HF gets updated only after a LOW-to-HIGH transition of the Read Clock RCLK, or else after a LOW-to-HIGH transition of the Write Clock WCLK, according to the setting of bits 03 and 02 of the Control Register (see Table 5). Thus, in this mode HF behaves as a `synchronous flag,' and may be synchronized either to the input side of the FIFO (i.e., to WCLK), or to the output side of the FIFO (i.e., to RCLK).
19
LH540235/45 PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) PAE goes LOW whenever the FIFO is `almost empty'; that is, whenever subtracting the value of the FIFO's internal write pointer from the value of its internal read pointer yields a difference which is less than q + 1, where `q' is the value of the Programmable-Almost-Empty-Flag Offset. The subtraction is performed using modular arithmetic, modulo the total nominal number of 18-bit words in the FIFO's physical memory, which is 2048 for the LH540235 or 4096 for the LH540245 respectively. The default value of q after the completion of a reset operation is 12710. However, q may be set to any value which does not exceed this total nominal number of words for the device, as explained in the description of Load (LD). If the FIFO has been reset by asserting RS (LOW), and no write operations have been performed since the completion of the reset operation, then PAE is LOW (see Table 4). If q is still at its default value, PAE is LOW whenever the FIFO is from one-eighth full to completely empty. In the IDT-Compatible Operating Mode, PAE changes from HIGH to LOW only after a LOW-to-HIGH transition of the Read Clock RCLK, and from LOW to HIGH only after a LOW-to-HIGH transition of the Write Clock WCLK. Thus, in this operating mode, PAE behaves as an `asynchronous flag.'
2048 x 18/4096 x 18 Synchronous FIFOs (RXO) signal to coordinate writing operations with the next FIFO in the cascade. Under these same conditions, also, the dual purpose RXI/REN2 and WXI/WEN2 inputs behave as Read Expansion Input (RXI) and Write Expansion Input (WXI) signals respectively. When two or more LH540235 or LH540245 FIFOs are operating in IDT-compatible `cascaded' mode as a deeper `effective FIFO,' the dual-purpose RXI/REN2 and WXI/WEN2 inputs behave as Read Expansion Input (RXI) and Write Expansion Input (WXI) signals respectively. An IDT-style cascade of these FIFO devices has a `daisychain' ring configuration; the Read Expansion Input (RXI) of each FIFO is connected to RXO (RXO/EF2, behaving as RXO) of the previous FIFO in the ring, with RXI of the `first-load' or `master' FIFO being connected to RXO of the last FIFO so as to complete the ring. Similar connections are made for each FIFO in the ring, parallel to these RXO-to-RXI connections, for Write Expansion Input (WXI) and Write Expansion Output (WXO). When the last physical location has been read in a FIFO operating in IDT-style cascaded mode, a LOW-going pulse is emitted by that FIFO on its RXO output; otherwise, RXO remains constantly HIGH. This LOW-going RXO pulse serves as a `read token' in the token-passing FIFO-cascading scheme; it is passed on to the next FIFO in the ring via its RXI input. When this next FIFO receives the read token, it is activated for reading at the next valid RCLK. After a FIFO emits an RXO pulse, the FIFO is deactivated for reading at the next valid RCLK. Also, its data outputs go into high-Z state, regardless of the assertion or deassertion of its Output Enable (OE) control input, until it again receives the token. Simultaneously, the next FIFO in the ring is activated for reading. The foregoing description applies both to the `first-load' or `master' FIFO in the ring, and to any and all `slave' FIFOs in the ring. However, RXO has no necessary function for a FIFO which is operating in `standalone' mode. Consequently, in that mode, RXO is never asserted, and remains constantly HIGH. A FIFO is initialized into `standalone' mode, into `cascaded master' mode, or into `cascaded slave' mode according to the state of its WXI/WEN2, RXI/REN2, and FL/RT control inputs during a reset operation. It also may be forced into interlocked-paralleled mode by EMODE (see Table 1, Table 2, and Table 5).
In the Enhanced Operating Mode, on the other hand, PAE gets updated only after a LOW-to-HIGH transition of the Read Clock RCLK, and thus behaves as a `synchronous flag,' whenever Control Register bit 01 is HIGH (see Table 5).
EMPTY FLAG (EF) EF goes LOW whenever the FIFO is completely empty. That is, whenever the FIFO's internal read pointer has completely caught up with its internal write pointer; so that, if another word were to be read out, it would have to come from the physical memory location which is now in position to be written into by the next requested write operation. Read operations are inhibited whenever EF is LOW, regardless of the assertion or deassertion of Read Enable (REN). If the FIFO has been reset by asserting RS (LOW), and no write operations have been performed since the completion of the reset operation, then EF is LOW. (See Table 4.) EF gets updated after a LOW-to-HIGH transition of the Read Clock RCLK. READ EXPANSION OUT/EMPTY FLAG 2 (RXO/EF2) RXO/EF2 is a dual-purpose signal. In `standalone' operation, it has no function. In IDT-compatible `cascaded' operation, it behaves as a Read Expansion Output
BOLD ITALIC = Enhanced Operating Mode
In the Enhanced Operating Mode, RXO/EF2 behaves as a second Empty Flag EF2. EF2 is an exact duplicate of the main Empty Flag EF, except that it is delayed with respect to EF By one full cycle of the Read Clock RCLK.
20
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS
tRS
RS tRSS tRSR
REN, WEN, LD tRSF
EF, PAE tRSF
FF, PAF, HF tRSF OE = HIGH1 OE = LOW NOTES: 1. After reset, the outputs will be LOW if OE = LOW, and in a high-impedance state if OE = HIGH. 2. The clocks (RCLK, WCLK) may be free-running during a reset operation.
540235-5
Q0 - Q17
Figure 6. Reset Timing
tCLK tCLKH tCLKL
WCLK tDS tDH
D0 - D17
VALID DATA IN
tENS tENH
WEN tWFF tWFF
NO OPERATION
FF tSKEW1(1)
RCLK
REN NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change predictably during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then it is not guaranteed that FF will change state until the next following WCLK edge.
540235-6
Figure 7. Synchronous Write Operation
21
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
tCLK tCLKH RCLK tENS tENH tCLKL
REN tREF
NO OPERATION tREF
EF tA
Q0 - Q17 tOLZ tOE
VALID DATA OUT
tOHZ
OE tSKEW2 (1)
WCLK
WEN NOTE: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change predictably during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then it is not guaranteed that EF will change state until the next following RCLK edge.
540235-7
Figure 8. Synchronous Read Operation
22
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS (cont'd)
WCLK tDS
D0 - D17 tENS
D0 (FIRST VALID WRTE)
D1
D2
D3
D4
WEN tFRL (2)
RCLK tSKEW2 (1) tREF
EF
REN tA (3) tA
Q0 - Q17 tOLZ tOE
D0
D1
OE
NOTES: 1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change predictably during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then it is not guaranteed that FF will change state until the next following WCLK edge. 2. tFRL (First-Read Latency) is the minimum time between a rising WCLK edge and a rising RCLK edge to assure a correct readout of the first data word D0 in response to the next RCLK edge. Thus, tFRL = tCLK + tSKEW2. If tFRL is not met, D0 may be available either at tCLK + tSKEW2, or after one more clock cycle delay at 2 tCLK + tSKEW2. The First-Read Latency timing restrictions apply only when the FIFO has been empty (EF = LOW). 3. EF may be used to determine when the first data word D0 may be read. D0 always is available on the next cycle after EF has gone HIGH.
540235-8
Figure 9. Latency for the First Data Word After a Reset Operation, With Simultaneous Read and Write
23
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
NO WRITE NO WRITE
WCLK tSKEW11 tDS tSKEW11 tDS DATA WRITE D0 - D17 tWFF DATA WRITE tWFF tWFF
FF
WEN
RCLK tENS tENH tENS tENH
REN OE LOW tA tA
Q0 - Q17
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change predictably during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then it is not guaranteed that FF will change state until the next following WCLK edge.
540235-9
Figure 10. Full-Flag Timing
24
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS (cont'd)
WCLK tDS tDS
D0 - D17 tENS
DATA WRITE 1
DATA WRITE 2
tENH tENH tENS
WEN tFRL(2) tSKEW2(1) tSKEW2(1) tFRL(2)
RCLK tREF tREF tREF tREF tREF
EF
EF2
REN
OE
LOW tA
Q0 - Q17
DATA IN OUTPUT REGISTER
DATA READ
NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change predictably during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then it is not guaranteed that EF will change state until the next following RCLK edge. 2. tFRL (First-Read Latency) is the minimum time between a rising WCLK edge and a rising RCLK edge to assure a correct readout of the first data word D0 in response to the next RCLK edge. Thus, tFRL = tCLK + tSKEW2. If tFRL is not met, D0 may be available either at tCLK + tSKEW2, or after one more clock cycle delay at 2 tCLK + tSKEW2. The First-Read Latency timing restrictions apply only when the FIFO has been empty (EF = LOW). 3. EF may be used to determine when the first data word D0 may be read. D0 always is available on the next cycle after EF has gone HIGH.
BOLD ITALIC = Enhanced Operating Mode.
540235-10
Figure 11. Empty-Flag Timing
25
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
t CLK tCLKH tCLKL
WCLK tENS tENH
LD tENS
WEN tDS
tDH D0 - D15 PAE OFFSET
CONTROL REGISTER
PAF OFFSET
540235-11
Figure 12. Programmable-Register Write Operation
t CLK tCLKH tCLKL
RCLK tENS tENH
LD tENS
REN tA CONTROL REGISTER Q0 - Q15 UNKNOWN PAE OFFSET PAF OFFSET
540235-12
Figure 13. Programmable-Register Read Operation
26
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS (cont'd)
tCLKH tCLKL
WCLK tENS tENH
WEN tPAE
PAE
q + 1 words in FIFO tPAE
q words in FIFO
RCLK tENS
REN NOTE: 1. PAE offset = q. Also, number of data words written into FIFO already = q.
540235-13
Figure 14. Programmable-Almost-Empty Flag Timing, IDT-Compatible Operating Mode
27
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
Enhanced Operating Mode Timing Diagram
A WCLK tDS tDS C
D0 - D17
DATA WRITE 1
DATA WRITE 2
tENS tENH tENS
tENH
WEN tSKEW2(1) B RCLK tPAES tPAES tPAES tSKEW2(1)
PAE
REN
OE
LOW tA
Q0 - Q17
DATA IN OUTPUT REGISTER
DATA READ
NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change predictably during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then it is not guaranteed that PAE will change state until the next following RCLK edge. 2. PAE offset = q. Also, number of data words written into FIFO already = q. 3. The internal state of the FIFO: At A , q+1 words. At B , q words. At C , q+1 words again.
540235-23
Figure 15. Programmable-Almost-Empty Flag Timing, When Synchronous (Enhanced Operating Mode)
28
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS (cont'd)
tCLKH tCLKL
WCLK tENS (1) tENH
WEN tPAF 2048 - p words in FIFO (2) tPAF
PAF
2047 - p words in FIFO (3)
RCLK tENS
REN
NOTES: 1. PAF offset = p. Number of data words written into FIFO already = 2047 - p for the LH540235 and 4095 - p for the LH540245. 2. 2048 - p words in FIFO for LH540235. 4096 - p words in FIFO for LH540245. 3. 2047 - p words in FIFO for LH540235. 4095 - p words in FIFO for LH540245.
540235-14
Figure 16. Programmable Almost-Full-Flag Timing, IDT-Compatible Operating Mode
29
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
Enhanced Operating Mode Timing Diagram
NO WRITE WCLK tSKEW1(1) tDS tSKEW1(1) tDS DATA WRITE D0 - D17 DATA WRITE tPAFS tPAFS tPAFS NO WRITE
B
PAF
WEN A RCLK tENS tENH tENS tENH C
REN OE LOW tA tA
Q0 - Q17
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change predictably during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then it is not guaranteed that PAF will change state until the next following WCLK edge. 2. PAF offset = p. Number of data words written into FIFO already = 2047 - p for the LH540235 and 4095 - p for the LH540245. 3. The internal state of the FIFO: At A , 2047 - p words in FIFO for LH540235 and 4095 - p words in FIFO for LH540245. At B , 2048 - p words in FIFO for LH540235 and 4096 - p words in FIFO for LH540245. At C , again 2047 - p words in FIFO for LH540235 and 4095 - p words in FIFO for LH540245.
540235-24
Figure 17. Programmable-Almost-Full-Flag Timing, When Synchronous (Enhanced Operating Mode)
30
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS (cont'd)
tCLKH tCLKL
WCLK tENS tENH
WEN tHF HALF FULL +1 OR MORE tHF
HF
HALF FULL OR LESS
HALF FULL OR LESS
RCLK tENS
REN
540235-15
Figure 18. Half-Full-Flag Timing, IDT-Compatible Operating Mode
31
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
Enhanced Operating Mode Timing Diagram
NO WRITE WCLK tSKEW11 tDS tSKEW11 tDS DATA WRITE D0 - D17 DATA WRITE tHFS tHFS tHFS NO WRITE
B
HF
WEN A RCLK tENS tENH tENS tENH C
REN OE LOW tA tA
Q0 - Q17
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for HF to change predictably during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then it is not guaranteed that HF will change state until the next following WCLK edge. 2. The internal state of the FIFO: At A , exactly half full. At B , half+1 words.
540235-25
At C , exactly half full again.
Figure 19. Half-Full-Flag Timing, When Synchronized to Input Port (Enhanced Operating Mode)
32
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS (cont'd)
Enhanced Operating Mode Timing Diagram
A WCLK tDS tDS C
D0 - D17 tENS
DATA WRITE 1
DATA WRITE 2
tENH tENH tENS
WEN tSKEW2(1) B RCLK tHFS tHFS tHFS tSKEW2(1)
HF tENS tENH
REN
OE
LOW tA
Q0 - Q17
DATA IN OUTPUT REGISTER
DATA READ
NOTE: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for HF to change predictably during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then it is not guaranteed that HF will change state until the next following RCLK edge. 2. The internal state of the FIFO: At A , half+1 words. At B , exactly half full. At C , half+1 words again.
540235-26
Figure 20. Half-Full-Flag Timing, When Synchronized to Output Port (Enhanced Operating Mode)
33
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
Q [17:0] tA
DR1 tA
DR2 tA
DRT12 tA
DRT2
RCLK R1 REN1 R2 RT1 RT2 RT3
A RT4
B
FL/RT tENH tENS PREVIOUS VALID FF FF tPAF PREVIOUS VALID PAF PAF tHF PREVIOUS VALID HF HF PREVIOUS VALID PAE PAE tPAE PREVIOUS VALID EF EF tREF NOTES: 1. It is not necessary for REN to be LOW for the device to recognize a retransmit request. 2. In order to actually read data words from the memory arrary, in IDT-Compatible Operating Mode, REN = LOW; in Enhanced Operating Mode, also REN2 = HIGH (and OE = LOW, if Control Register bit 05 = HIGH). In any case, LD = HIGH. 3. DRT1 is the data item in physical location zero of the FIFO memory array. 4. The asynchronous intermediate flags (corresponding to LOW Control-Register bits) will show correct status three RCLK cycles after a retransmit operation, as is shown above. (RT3, in the above RCLK waveform.) 5. The intermediate flags which have been synchronized to RCLK, by setting the appropriate Control-Register bits to HIGH will show correct status after B , four RCLK cycles after a retransmit operation. (RT4, in the above RCLK waveform.) 6. The intermediate flags which have been synchronized to WCLK, by setting the appropriate Control-Register bits HIGH, will show correct status on the second WCLK rising edge after A , assuming that tSKEW1 was satisfied at A ; otherwise the flags will become valid on the third WCLK rising edge after A . 7. Immediately after a reset operation, before any write operations have taken place, a retransmit operation is a 'no-op', and does not change the state of any FIFO registers or flags. 8. In the special case that the FIFO memory array contains only one valid data item, the status of HF and PAF should be ignored on a retransmit. NEW VALID EF UNKNOWN NEW VALID PAE UNKNOWN NEW VALID HF UNKNOWN NEW VALID PAF tRSF tENS tWFF NEW VALID FF
540235-28
Figure 21. Retransmit Timing, IDT-Compatible Operating Mode 34
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
TIMING DIAGRAMS (cont'd)
tCLKH
WCLK
(NOTE)
tXO
tXO
WXO tENS
WEN NOTE: Write to last physical location.
540235-16
Figure 22. Write-Expansion-Out Timing, IDT-Compatible Operating Mode
tCLKH
RCLK
(NOTE)
tXO
tXO
RXO tENS
REN NOTE: Read from last physical location.
540235-17
Figure 23. Read-Expansion-Out Timing, IDT-Compatible Operating Mode
tXI
WXI tXIS
WCLK
540235-18
Figure 24. Write-Expansion-In Timing,
35
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont'd)
tXI
RXI tXIS
RCLK
540235-19
Figure 25. Read-Expansion-In Timing, IDT-Compatible Operating Mode
APPLICATIONS INFORMATION
Standalone Configuration When depth cascading is not required for a given application, the LH540235/45 is placed in standalone mode by tying the two Expansion In pins WXI/WEN2 and RXI/REN2 to ground, while also holding the First Load/Retransmit pin FL/RT LOW for the duration of any reset operation. (See Table 1.) Subsequently, FL/RT may be taken HIGH at will, whenever a retransmit operation is desired. If not being used, FL/RT also may be tied to ground, as shown in Figure 27.
RESET (RS)
Width Expansion Word-width expansion is implemented by placing multiple LH540235/45 devices in parallel. Each device should be configured for standalone mode, unless the depth of one single FIFO is not adequate for the application. In this event, word-width expansion may in principle be used with either of the two depth-cascading schemes supported by the LH540235/45 architecture. In practice, the reliability benefits of interlocked-paralleled operation are available only with the pipelining scheme, making it the preferred alternative. (Refer to discussion in a later section.)
ENHANCED MODE (EMODE)
WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) DATA IN FULL FLAG (FF) PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) HALF-FULL FLAG (WXO/HF) FIRST LOAD (FL/RT) (MUST BE LOW DURING A RESET OPERATION) 18 LH540235/45 D[17:0] Q[17:0] 18
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) DATA OUT EMPTY FLAG (EF) PROGRAMMABLE ALMOST-FULL FLAG (PAF)
WRITE EXPANSION IN (WXI/WEN2) READ EXPANSION IN (RXI/REN2)
BOLD ITALIC = Enhanced Operating Mode.
540235-21
Figure 26. Standalone FIFO (2048 x 18 / 4096 x 18)
BOLD ITALIC = Enhanced Operating Mode
36
2048 x 18/4096 x 18 Synchronous FIFOs When standalone-mode LH540235/45 devices are paralleled, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive `composite' flag values using external logic, since there may be minor speed variations between different actual devices. After writing or reading have been in a disabled state, the process of re-enabling should be gated by the slowest FIFO. For m paralleled FIFOs, the form of this external composite-flag logic may be an OR gate with m assertive-LOW inputs and an assertive-LOW output. In keeping with deMorgan's Theorem, such a gate may be implemented as an AND gate with m assertive-HIGH inputs and an assertive-HIGH output. Figure 28 illustrates the case m = 2. The LH540235/45 architecture supports two very different methods of depth cascading: Token passing, which follows the scheme used in the pin-compatible and functionally-compatible Integrated Device Technology IDT72205B/15B/25B/35B/45B FIFOs, which the LH540235/45 can directly replace. Pipelining, which follows the scheme used in the Texas Instruments SN74ACT7801/11/81/82/84 FIFOs, and also in the Sharp LH543620 1024 x 36 FIFO. The SN74ACT7801/11/81/82/84 pinout closely resembles the LH540235/45 pinout, but is not identical. Depth Cascading Using Token Passing Using the token-passing approach, depth cascading is implemented by configuring the required number of LH540235/45s in a circular `ring' fashion, with the Expansion Out outputs (WXO/HF and RXO/EF2) of each device tied to the Expansion In inputs (WXI/WEN2 and RXI/REN2) of the next device (see Figure 29). Because a reset operation forces the WXO/HF and RXO/EF2 outputs HIGH for each device, the WXI/WEN2 and RXI/REN2 inputs for the next device are HIGH during the reset operation; thus, these two inputs are HIGH for all devices in the ring. (See Tables 1 and 2, and also Figure 29.) All devices in the cascade must be in the IDT-Compatible Operating Mode; thus, their EMODE inputs must be tied to Vcc.
LH540235/45 One FIFO in the cascade must be designated as the `first-load' device, by tying its First Load input (FL/RT) to ground. All other devices must have their FL/RT inputs tied HIGH. Under these circumstances, the Retransmit function is not available for use. In this mode, the control inputs which govern writing (WCLK and WEN) and the control inputs which govern reading (RCLK and REN) are shared by all devices, while logic within each LH540235/45 governs the steering of data. The common Data Inputs of all devices are tied together; but only one LH540235/45 is enabled during any given write cycle. Likewise, the common three-state Data Outputs of all devices are wire-ORed together; but only one LH540235/45 is enabled, including its threestate outputs, during any given read cycle. A data word is handled only by one device as it passes through the cascade of FIFOs, regardless of how many FIFOs are being cascaded together. In the token-passing depth-cascaded mode, external logic should be used to generate a composite Full Flag and a composite Empty Flag, by ANDing the FF outputs of all LH540235/45 devices together and by ANDing the EF outputs of all devices together, using AND gates with assertive-LOW inputs and an assertive-LOW output. Here, the meaning of these composite flags is direct: the cascade of FIFOs is full, if and only if all k FIFOs belonging to the cascade are individually full; and similarly for empty. In keeping with deMorgan's Theorem, these k-input assertive-LOW AND gates are implemented physically as k-input assertive-HIGH OR gates. Figure 29 illustrates the case k = 3. Similar external logic also may be used to generate a composite Programmable Almost-Full Flag and a composite Programmable Almost-Empty Flag, by ANDing the PAF outputs of all LH540235/45 devices together and by ANDing the PAE outputs of all devices together. Here, however, some careful analysis is required, to determine exactly what the resulting composite flags mean. Their significance may vary widely, depending on the number of FIFOs in the cascade, and on the `offset' values which are present in the offset registers for these FIFOs. More complex logical combinations of PAF outputs with FF outputs, and of PAE outputs with EF outputs, may be found useful in particular applications. In any case, the Half-Full Flag and the Retransmit function are not available for devices being used in tokenpassing depth-cascaded mode.
BOLD ITALIC = Enhanced Operating Mode
37
38
HFC
HF WCLK RCLK REN WEN LD RS OE Q[17:0] PAE EF
LH540235/45
EF2
WRITE CLOCK
READ CLOCK READ ENABLE
WRITE ENABLE
EMODE
LOAD
OUTPUT ENABLE 18
18
D[17:0] PAF FF FL/RT WEN2 REN2
FFC
EFC
DATA IN
HF WCLK WEN LD RS
36
EF2
RCLK REN
36
DATA OUT
Figure 27. Interlocked-Paralleled Word-Width Expansion
EMODE
OE
RESET 18
D[17:0] PAF FF
Q[17:0] PAE EF FL/RT WEN2 REN2
18 PAEC
PAFC
RETRANSMIT (MUST BE LOW DURING A RESET OPERATION
2048 x 18/4096 x 18 Synchronous FIFOs
NOTE: BOLD ITALIC = Enhanced Operating Mode.
540235-32
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
WRITE-TOKEN PULSE READ-TOKEN PULSE
WXO RXO WCLK RCLK WEN LD RS REN
EMODE
OE Q[17:0] PAE EF WXI RXI
VCC
18
D[17:0] PAF FF FL
18
VCC
WXO RXO WCLK RCLK WEN LD RS REN
EMODE
OE Q[17:0] PAE EF WXI RXI
VCC
18
18
DATA IN
D[17:0] PAF FF FL
DATA OUT
18
18
VCC WRITE CLOCK WRITE ENABLE RESET LOAD 18
WXO RXO WCLK RCLK WEN LD RS D[17:0] PAF REN
READ CLOCK READ ENABLE
VCC OUTPUT ENABLE
EMODE
OE Q[17:0] PAE
18
FF (COMPOSITE FLAGS) PAF
EF FF FL WXI RXI
EF (COMPOSITE FLAGS) PAE
FIRST LOAD
NOTES: Grounding FL designates the 'first-load' FIFO ('master' FIFO). The remaining FIFOs are 'slave' FIFOs. BOLD ITALIC = Enhanced Operating Mode.
540235-27
Figure 28. Synchronous-FIFO Depth-Cascading Using IDT-Compatible `Token-Passing' Scheme
39
LH540235/45 Depth Cascading Using Pipelining Using the pipelining approach, depth cascading is implemented by connecting the required number of LH540235/45s in series. Within the cascade, the Data Outputs of each device are connected to the Data Inputs of the next device. (See Figure 30.) All devices in the cascade must be in the Enhanced Operating Mode; thus, their EMODE inputs must be grounded. Successive devices in the cascade are crosscoupled; they control each other, using a `handclasp' scheme for crossconnecting their control inputs and their status outputs. (See again Figure 30.) The input side of the first device, and the output side of the last device, are not crosscoupled to other devices. Their control/status and clock pins are connected to the external system. For the FIFO devices within the cascade, transferring data from each device to the next device is governed by a clock. Preferably, the same clock should be used at every FIFO-to-FIFO data-transfer interface boundary within the cascade. This `Transfer Clock' may be either the external Write Clock, or the external Read Clock. If both of these two clocks are periodic and free-running, the faster of the two is the obvious choice for the `Transfer Clock.' Of course, in principle, the `Transfer Clock' may even be some other, totally-different clock. The Empty Flag of each device is used to govern writing into the next device, and the Full Flag of each device is used to govern reading from the preceding device. Since the standard Empty Flag EF occurs one RCLK cycle too early to properly enable/disable the next device, the duplicate Empty Flag EF2 is used instead; EF2 is an exact copy of EF, except that it is delayed by one full RCLK cycle with respect to EF. Also, since the usual enable signals WEN and REN have the wrong polarity to function properly in this `handclasp' mode, they are grounded for all devices within the cascade. The duplicate but inverted signals WEN2 and REN2 are used instead.
2048 x 18/4096 x 18 Synchronous FIFOs When all of the foregoing conditions have been met in the interconnection of the pipelined array, then: At each device-to-device interface boundary within the array, a data word is transferred from the upstream device to the downstream device after every transfer-clock rising edge, as long as the upstream device is not empty and the downstream device is not full. Width Expansion Along With Depth Cascading In principle, width expansion may be used with either of the two possible depth-cascading schemes. However, when using the token-passing depth-cascading scheme, width expansion reduces simply to placing two or more cascades in parallel. In this mode of interconnection, no architectural support is available for interlocked-paralleled operation. Composite-flag logic may, of course, be designed to fit any complete array configuration, to determine meaningful full and empty indications for the entire array. This logic may, for instance, OR the FF and EF signals from the devices at the same relative position in each of the paralleled cascades, and then AND all of the rank-FF signals together; and likewise for all of the rank-EF signals. Then, the entire array is indicated to be full, if all ranks of devices (across the paralleled cascades) are individually full; and, similarly for empty. When using the pipelined depth-cascading scheme, on the other hand, the first rank of devices (the one which receives input data words from the external system) and the last rank of devices (the one which provides output data words to the external system) may be operated in an interlocked-paralleled manner. Figure 31 shows a suggested interconnection scheme for two paralleled cascades, each three devices deep. The entire array of Figure 31 would comprise a 12288 x 36 `effective FIFO,' if implemented with 4096 x 18 LH540245 devices. Whenever the number of paralleled cascades exceeds two, a small amount of external logic is necessary to implement the interlocking.
EF2, WEN2, and REN2 are available only in Enhanced Operating Mode. They share the same pins which in IDT-Compatible Operating Mode are used respectively for RXO, WXI, and RXI. Hence, for pipelined operation, all devices in the cascade must be in the Enhanced Operating Mode; their EMODE control inputs must be grounded.
BOLD ITALIC = Enhanced Operating Mode
40
TRANSFER CLOCK
HF WCLK RCLK REN WEN VCC RS OE Q[17:0] PAE EF LD REN WCLK RCLK WEN LD VCC RS OE Q[17:0] PAE EF FL WEN2 REN2 FF PAF
EF2
HF
EF2
HF
EF2
RCLK REN READ CLOCK READ ENABLE
2048 x 18/4096 x 18 Synchronous FIFOs
WRITE CLOCK
WCLK WEN LD RS
WRITE ENABLE
LOAD
EMODE
EMODE
EMODE
OE OUTPUT ENABLE
DATA IN D[17:0] PAF FF FL WEN2 REN2 VCC D[17:0]
18
18
18
D[17:0] PAF FF
Q[17:0] PAE EF FL WEN2 REN2
18
DATA OUT ALMOST EMPTY EMPTY
ALMOST FULL
FULL
Figure 29. TI-Style Pipelined Depth-Cascading
VCC
RESET
NOTES:
The transfer clock may be any free-running clock. However, it is recommended that the faster of the Write Clock and the Read Clock be used, if both of these are free-running clocks.
540235-30
LH540235/45
BOLD ITALIC = Enhanced Operating Mode.
41
42
HF WCLK RCLK REN WEN VCC RS OE Q[17:0] PAE PAF FF EF EF PAE EFC 18 D[17:0] Q[17:0] 18 OE 18 D[17:0] PAF FF FL WEN2 REN2 RS LD REN WEN VCC LD REN WCLK RCLK RCLK WCLK WEN LD RS OE Q[17:0] PAE EF 18 D[17:0] PAF FF FL WEN2 REN2
TRANSFER CLOCK
LH540235/45
EF2
HF
EF2
HF
EF2
READ CLOCK READ ENAB LE
WRITE CLOCK
WRITE ENABLE
LOAD
EMODE
EMODE
EMODE
FFC
FL WEN2 REN2
DATA IN
36
36
DATA OUT
HF WCLK RCLK REN WEN VCC LD RS 18 D[17:0] PAF FF WCLK WEN LD RS 18 D[17:0] PAF PAE EF FF FL WEN2 REN2 Q[17:0] OE
EF2
HF
EF2
RCLK REN
HF WCLK WEN
EF2
RCLK REN
EMODE
EMODE
OE Q[17:0] PAE EF FL WEN2 REN2
VCC
LD RS 18 D[17:0] PAF FF
EMODE
OE Q[17:0] PAE EF FL WEN2 REN2 18
Figure 30. Interlocked Paralleling Used Together With Pipelined Depth-Cascading
RESET
NOTES:
The transfer clock may be any free-running clock. However, it is recommended that the faster of the Write Clock and the Read Clock be used, if both of these are free-running clocks.
540235-33
2048 x 18/4096 x 18 Synchronous FIFOs
BOLD ITALIC = Enhanced Operating Mode.
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
PACKAGE DIAGRAMS
68PLCC (PLCC68-P-950)
24.23 [0.954] 24.13 [0.950] 25.27 [0.995] 25.02 [0.985] 23.62 [0.930] 22.61 [0.890]
24.23 [0.954] 24.13 [0.950] 25.27 [0.995] 25.02 [0.985] 3.91 [0.154] 3.71 [0.146] 4.57 [0.180] 4.19 [0.165]
0.10 [0.004] 1.27 [0.050] BSC 0.53 [0.021] 0.33 [0.013] MAXIMUM LIMIT MINIMUM LIMIT 0.051 [0.020] MIN
DIMENSIONS IN MM [INCHES]
68PLCC-1
68-Pin PLCC
43
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
64TQFP (TQFP-64-P-1414) DETAIL
0.20 [0.008] 0.09 [0.004]
0.75 [0.030] 0.45 [0.018]
0.15 [0.006] 0.05 [0.002]
16.0 [0.630] BASIC 14.0 [0.551] BASIC
16.0 [0.630] BASIC
14.0 [0.551] BASIC
0.80 [0.031] BASIC
1.60 [0.063] MAX.
1.45 [0.057] 1.35 [0.53]
0.45 [0.018] 0.30 [0.012]
0.10 [0.004]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
64TQFP
64-Pin TQFP
44
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
ORDERING INFORMATION
LH540235/45 Device Type X Package - ## Speed 20 25 Cycle Time (ns) 35 U 68-Pin Plastic Leaded Chip Carrier (PLCC68-P-S950) M 64-Pin Thin Quad Flat Package 2048 x 18/4096 x 18 Synchronous FIFO Example: LH540245U-20 (4096 x 18 Sychronous FIFO, 20 ns, 68-pin PLCC)
540235MD
45
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
BOLD ITALIC = Enhanced Operating Mode
46

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